Architectural exploration and implementation of power analysis attack tolerant block ciphers from specifications to silicon

Abstract

Cryptography which provides the required data security and privacy is inevitable in most of the applications in today s world. Cryptographic algorithms are employed to accomplish the same by using either a single secret key in the name of private or symmetric key cryptography, or by using a public and private key pair in the name of public or asymmetric key cryptography. The private key cryptographic algorithms are faster and computationally less intensive than the public key algorithms. Hence, this thesis has focussed on the same. Among the software and hardware realizations of the algorithms, the hardware realization in-terms of dedicated crypto accelerators or hardware security modules are preferred to achieve better area and performance. Though there exists a wide range of symmetric key ciphers in literature, National Institute of Standards and Technology (NIST) has standardised the Advanced Encryption Standard (AES) which is adopted in many practical applications. For resource constrained applications like smart cards, Radio Frequency Identification Tags (RFID) etc., recent literature has explored a new category of symmetric key algorithms, in the name of lightweight ciphers. CLEFIA is one such lightweight block cipher which is standardized by International Organization for Standardization/International Electrotechnical Commission (ISO/IEC) 29192-2. Hence, this thesis has adopted the AES algorithm for the standard block cipher category and the CLEFIA algorithm for the lightweight block cipher category. The first part of this thesis aims to develop novel hardware architectures by realizing the sub blocks of the algorithm in a unique manner. newline