1. Shodhganga@INFLIBNET
  2. Sathyabama Institute of Science and Technology
  3. ELECTRONICS DEPARTMENT
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/517090
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-10-10T06:23:04Z-
dc.date.available2023-10-10T06:23:04Z-
dc.identifier.urihttp://hdl.handle.net/10603/517090-
dc.format.extentvi, 138
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlePower reduction methodologies for Testing low power VLSI circuits
dc.title.alternative
dc.creator.researcherWARADE NILIMA SATISH
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideRavi T
dc.publisher.placeChennai
dc.publisher.universitySathyabama Institute of Science and Technology
dc.publisher.institutionELECTRONICS DEPARTMENT
dc.date.registered2013
dc.date.completed2021
dc.date.awarded2023
dc.format.dimensionsA5
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:ELECTRONICS DEPARTMENT

Files in This Item:
File Description SizeFormat 
10.chapter 6.pdfAttached File131.11 kBAdobe PDFView/Open
11.annexure.pdf1.76 MBAdobe PDFView/Open
1.title.pdf19.39 kBAdobe PDFView/Open
2.prelim pages.pdf944.33 kBAdobe PDFView/Open
3.abstract.pdf11.87 kBAdobe PDFView/Open
4.contents.pdf154.61 kBAdobe PDFView/Open
5.chapter 1.pdf223.21 kBAdobe PDFView/Open
6.chapter 2.pdf244.83 kBAdobe PDFView/Open
7.chapter 3.pdf1.09 MBAdobe PDFView/Open
80_recommendation.pdf19.39 kBAdobe PDFView/Open
8.chapter 4.pdf1.06 MBAdobe PDFView/Open
9.chapter 5.pdf1.02 MBAdobe PDFView/Open
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