Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/516711
Title: Efficient parallel architecture for optimizing performance in SoCs
Researcher: Mitra, Ved
Guide(s): Govil, Mahesh Chandra and Singh, Girdhari
Keywords: Computer Science
Computer Science Information Systems
Engineering and Technology
Low-Density Parity-Check Codes
System-on-a-chip (SoC) designs
University: Malaviya National Institute of Technology Jaipur
Completed Date: 2022
Abstract: newline
Pagination: xvii,89p.
URI: http://hdl.handle.net/10603/516711
Appears in Departments:Department of Computer Science and Engineering

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01_title.pdfAttached File274.6 kBAdobe PDFView/Open
02_prelims pages.pdf3.9 MBAdobe PDFView/Open
03_contents.pdf370.7 kBAdobe PDFView/Open
04_abstract.pdf622.04 kBAdobe PDFView/Open
05_chapter1.pdf747.28 kBAdobe PDFView/Open
06_chapter2.pdf1.4 MBAdobe PDFView/Open
07_chapter3.pdf1.24 MBAdobe PDFView/Open
08_chapter4.pdf1.33 MBAdobe PDFView/Open
09_chapter5.pdf1.22 MBAdobe PDFView/Open
10_chapter6.pdf603.57 kBAdobe PDFView/Open
11_annexures.pdf1.44 MBAdobe PDFView/Open
80_recommendation.pdf876.85 kBAdobe PDFView/Open
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