Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/516195
Title: | Design and analysis of clock gating Elements for energy efficient Implementations on fpga |
Researcher: | Agnes shiny Rachel, N |
Guide(s): | Rajakumar, G |
Keywords: | clock gating Design and analysis Engineering Engineering and Technology Engineering Electrical and Electronic fpga |
University: | Anna University |
Completed Date: | 2022 |
Abstract: | Signal processing is the need of the day for areas such as newlinebiomedical analysis and video processing applications etc. This is because in newlineall imaginable fields, signals are used to transmit information. Signal newlineprocessing is used in communication, to improve the quality of audio and newlinevideo, for security purposes in detecting weapons and most importantly in newlinemedical diagnosis. Therefore researches focusing on signal processing serve newlineas an essential contribution in improving the world on whole. Filter is a part newlineof the signal processing circuit that helps in improving the quality of the newlineincoming signal by removing the unwanted noise and frequencies. Filter newlinedesign therefore has to be taken care and filters should be constructed with newlineprecise device parameters which can enable efficient removal of background newlinenoise and improve quality of the input signals. In addition to this, in the fast newlinegrowing Very Large Scale Integration (VLSI) era, all circuits are expected to newlineoperate with low power utilization. Design of an authenticated low power newlineFinite Impulse Response (FIR) filter hence has become an area of intense newlineresearch concern. In the recent years, Least Mean Square (LMS) filter design newlinehas been used for various applications. The first contribution proposed in newlinethis research work aims at creating a novel structure for a power efficient newlineadaptive Finite Impulse Response Least Mean Square FIR LMS filter to newlineprocess signals. The filter design is improved with inclusion of the Coordinate newlineRotation Digital Computer (CORDIC) multiplier architecture that newlineuses simple Shift and add mechanism for computation, reducing area and newlinedelay of the design when compared with the conventional multiplication newlinetechniques. newline newline |
Pagination: | xx,139p. |
URI: | http://hdl.handle.net/10603/516195 |
Appears in Departments: | Faculty of Information and Communication Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 29.65 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 2.09 MB | Adobe PDF | View/Open | |
03_content.pdf | 28.93 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 31.36 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 249.08 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 369.77 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 1.13 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 514.61 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 401.65 kB | Adobe PDF | View/Open | |
10_annexures.pdf | 139.21 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 88.41 kB | Adobe PDF | View/Open |
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