1. Shodhganga@INFLIBNET
  2. Karpagam University
  3. Electronics
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/515819
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-10-04T06:14:55Z-
dc.date.available2023-10-04T06:14:55Z-
dc.identifier.urihttp://hdl.handle.net/10603/515819-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleDesign And Implementation Of Improved Low Power Vedic Multiplier With Reversible Logic
dc.title.alternative
dc.creator.researcherHRIDYA S
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guide
dc.publisher.placeCoimbatore
dc.publisher.universityKarpagam University
dc.publisher.institutionElectronics
dc.date.registered2018
dc.date.completed2021
dc.date.awarded2022
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics

Files in This Item:
File Description SizeFormat 
80_recommendation.pdfAttached File764.23 kBAdobe PDFView/Open
abstract.pdf83.35 kBAdobe PDFView/Open
certificate.pdf155.71 kBAdobe PDFView/Open
chapter 3.pdf824.15 kBAdobe PDFView/Open
chapter 4.pdf626.57 kBAdobe PDFView/Open
chapter 5.pdf1.81 MBAdobe PDFView/Open
chpater 2 litertaure review.pdf856.59 kBAdobe PDFView/Open
front page (2).pdf111.31 kBAdobe PDFView/Open
introduction.pdf641.46 kBAdobe PDFView/Open
reference.pdf393.78 kBAdobe PDFView/Open
table of contents.pdf162.98 kBAdobe PDFView/Open
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