Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/515819
Title: Design And Implementation Of Improved Low Power Vedic Multiplier With Reversible Logic
Researcher: HRIDYA S
Guide(s): 
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Karpagam University
Completed Date: 2021
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/515819
Appears in Departments:Electronics

Files in This Item:
File Description SizeFormat 
80_recommendation.pdfAttached File764.23 kBAdobe PDFView/Open
abstract.pdf83.35 kBAdobe PDFView/Open
certificate.pdf155.71 kBAdobe PDFView/Open
chapter 3.pdf824.15 kBAdobe PDFView/Open
chapter 4.pdf626.57 kBAdobe PDFView/Open
chapter 5.pdf1.81 MBAdobe PDFView/Open
chpater 2 litertaure review.pdf856.59 kBAdobe PDFView/Open
front page (2).pdf111.31 kBAdobe PDFView/Open
introduction.pdf641.46 kBAdobe PDFView/Open
reference.pdf393.78 kBAdobe PDFView/Open
table of contents.pdf162.98 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: