Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/515819
Title: | Design And Implementation Of Improved Low Power Vedic Multiplier With Reversible Logic |
Researcher: | HRIDYA S |
Guide(s): | |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Karpagam University |
Completed Date: | 2021 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/515819 |
Appears in Departments: | Electronics |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
80_recommendation.pdf | Attached File | 764.23 kB | Adobe PDF | View/Open |
abstract.pdf | 83.35 kB | Adobe PDF | View/Open | |
certificate.pdf | 155.71 kB | Adobe PDF | View/Open | |
chapter 3.pdf | 824.15 kB | Adobe PDF | View/Open | |
chapter 4.pdf | 626.57 kB | Adobe PDF | View/Open | |
chapter 5.pdf | 1.81 MB | Adobe PDF | View/Open | |
chpater 2 litertaure review.pdf | 856.59 kB | Adobe PDF | View/Open | |
front page (2).pdf | 111.31 kB | Adobe PDF | View/Open | |
introduction.pdf | 641.46 kB | Adobe PDF | View/Open | |
reference.pdf | 393.78 kB | Adobe PDF | View/Open | |
table of contents.pdf | 162.98 kB | Adobe PDF | View/Open |
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