Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/514650
Title: System verification
Researcher: Aghav, Jagannath Vithalrao
Guide(s): Shyamasundar, R K
Keywords: Computer Science
Computer Science Artificial Intelligence
Engineering and Technology
ESTEREL Basics
Reaction Cycle
Speedometer
TAXYS Validation
Time Markers
University: University of Mumbai
Completed Date: 2004
Abstract: No newline newline
Pagination: xiv, 154p
URI: http://hdl.handle.net/10603/514650
Appears in Departments:Computer Science, Tata Institute of Fundamental Research

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01_title.pdfAttached File296.96 kBAdobe PDFView/Open
02_prelim pages.pdf3.18 MBAdobe PDFView/Open
03_contents.pdf840.69 kBAdobe PDFView/Open
04_chapter 1.pdf2.59 MBAdobe PDFView/Open
05_chapter 2.pdf12.91 MBAdobe PDFView/Open
06_chapter 3.pdf2.62 MBAdobe PDFView/Open
07_chapter 4.pdf8.58 MBAdobe PDFView/Open
08_chapter 5.pdf3.25 MBAdobe PDFView/Open
09_chapter 6.pdf10.14 MBAdobe PDFView/Open
10_chapter 7.pdf3 MBAdobe PDFView/Open
11_annexures.pdf13.6 MBAdobe PDFView/Open
80_recommendation.pdf3.3 MBAdobe PDFView/Open
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