Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/512183
Title: A novel design of nano router with high speed crossbar scheduler for digital systems in qca paradigm
Researcher: Kalpana, K
Guide(s): Paulchamy, B and Jaya, J
Keywords: digital systems
Engineering
Engineering and Technology
Engineering Electrical and Electronic
nano router
qca paradigm
University: Anna University
Completed Date: 2023
Abstract: The work presented in this thesis focuses on employing Quantumdot newlineCellular Automata to create electronic logic circuits (QCA). The idea newlinedelves into the theory of QCA technology and terminology in depth. For a newlinemore in-depth understanding of the issue, several original concepts and newlineimplementations from the literature have been examined. It has been newlinediscovered that it is possible for novel QCA-based logic circuits and newlineapplications with enhanced circuit parameters such as area, circuit newlinecomplexity, and clock delays to be designed and implemented. This motivates newlineme to carry out the work that is part of this study program. It also includes an newlinein-depth examination of QCA circuits and a summary of current literature in newlinethis field. The importance of researching the thesis topic has been adequately newlinedemonstrated.I t has been discussed how to create QCA-based logic circuits newlineusing a combinational technique. Implementing a QCA-based three-input newlineXOR gate with enhanced circuit characteristics has been attempted. The newlinecombinational circuit, like a full adder and subtractor, is proposed based on newlinethree input XOR gates. This thesis considered typical circuit factors such as newlinedesign complexity, speed, and power consumption when submitting novel newlineQCA-based circuits. Before that, the low-power full adder is designed, and newlinethe performance metrics are analyzed using Multithreshold CMOS technology newlinein various regimes.A novel D flip-flop using the proposed QCA pulse generator newlinehas been implemented. Typically, 2-Bit and N-bit synchronous counters have newlinebeen submitted using proposed D flip-flop and pulse generator QCA circuits. newlineThe proposed circuit has been tested and analyzed their performance matrices. newlineA new architecture of the Nano router for high-speed data newlinetransmission has been implemented and presented in the thesis. To achieve newlineNano communication using the proposed circuit. The proposed course has newlinebeen developed with various modules like multiplexer, demultiplexer, switch newlinefabric, and parallel to serial converter. newline newline
Pagination: xv,114p.
URI: http://hdl.handle.net/10603/512183
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File71.19 kBAdobe PDFView/Open
02_prelim pages.pdf1.94 MBAdobe PDFView/Open
03_content.pdf10.88 kBAdobe PDFView/Open
04_abstract.pdf6.89 kBAdobe PDFView/Open
05_chapter 1.pdf26.45 kBAdobe PDFView/Open
06_chapter 2.pdf26.71 kBAdobe PDFView/Open
07_chapter 3.pdf264.81 kBAdobe PDFView/Open
09_chapter 5.pdf458.36 kBAdobe PDFView/Open
10_chapter 6.pdf191.64 kBAdobe PDFView/Open
11_chapter 7.pdf1.18 MBAdobe PDFView/Open
12_annexures.pdf66.87 kBAdobe PDFView/Open
80_recommendation.pdf85.45 kBAdobe PDFView/Open
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