Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/512128
Title: Studies on OPAMP Less Pipelined Analog to Digital Converter for Deep Submicron Technologies
Researcher: Singh, Anil
Guide(s): Agarwal, Alpana
Keywords: Analog electronic systems
Analog-to-digital converters
Digital electronics
Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Thapar Institute of Engineering and Technology
Completed Date: 2016
Abstract: Pipelined ADC is a popular choice for applications requiring high sampling rates of the range of 50-100 MHz and resolution of up to 12 bits typically which can be extended using different calibration techniques. Resolution is mainly limited by various non-idealities existing in a switched capacitor (SC) implementation of Pipelined ADC stage such as offset, capacitor mismatch, finite amplifier gain, amplifier non-linearity etc. These errors cause linear as well as non-linear errors in the ADC output; the effect of such errors can be mitigated using a calibration technique. So, it is important to understand the various errors, their sources and their impact on total ADC output. Therefore, various pipelined ADC errors occurring in a stage and their impact on overall ADC characteristics are modeled and analyzed using MATLAB. Targeting low power, low area and low cost, an opamp-less fully differential MOSFET-only pipelined ADC stage is presented in TSMC 0.18and#956;m digital CMOS technology with power supply of 1.8 V. It is based on 1.5-bit/stage architecture and uses the charge pump technique to achieve the inter stage gain of 2. Furthermore, stage is independent of capacitor mismatch and avoids the use of power hungry opamps thus reduces the power consumption and Silicon area. In the present research work, MOSCAPs are used in place of MIMCAPs to reduce the manufacturing cost and Silicon area further. Proposed MOSFET-only stage suffers from only gain error. A 10-bit 100 MS/s pipelined ADC is designed using the proposed stage and digital background calibration is performed to compensate the missing codes resulted from the gain error. Before calibration SNDR and SFDR of the pipelined ADC is 39.61 dB and 40.39 dB respectively which increase to 66.78 dB and 79.3 dB after calibration. Also DNL improves to +0.6/-0.4 LSB and INL improves from +9.3/-9.6 LSB to within ± 0.5 LSB. Total power consumption of the ADC is 16.53 mW. A design methodology is proposed to design the MOSFET-only charge pump based pipelined ADC. Following this, a MOSFET-only charge-pump based pipelined ADC can be designed with lesser iterations and design efforts, and reduces the time to market. Designing of various building blocks of the proposed stage along with the tradeoffs are discussed.
Pagination: 
URI: http://hdl.handle.net/10603/512128
Appears in Departments:Department of Electronics and Communication Engineering

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01_title.pdfAttached File103.08 kBAdobe PDFView/Open
02_prelim pages.pdf2.24 MBAdobe PDFView/Open
03_content.pdf265.58 kBAdobe PDFView/Open
04_abstract.pdf450.19 kBAdobe PDFView/Open
05_chapter 1.pdf2.54 MBAdobe PDFView/Open
06_chapter 2.pdf2.53 MBAdobe PDFView/Open
07_chapter 3.pdf12.63 MBAdobe PDFView/Open
08_chapter 4.pdf8.28 MBAdobe PDFView/Open
09_chapter 5.pdf4.08 MBAdobe PDFView/Open
10_chapter 6.pdf13.63 MBAdobe PDFView/Open
11_chapter 7.pdf744.5 kBAdobe PDFView/Open
12_annexures.pdf2.7 MBAdobe PDFView/Open
80_recommendation.pdf688.53 kBAdobe PDFView/Open
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