1. Shodhganga@INFLIBNET
  2. Rajiv Gandhi Proudyogiki Vishwavidyalaya
  3. Department of Electronic & Instrumentation
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/509823
Title: Some Techniques for Power Optimization in Fast Settling CMOS OPAMP
Researcher: Chandrawat,Uday Bhanu Singh
Guide(s): Mishra, D.K.
Keywords: Engineering
Engineering and Technology
Instruments and Instrumentation
University: Rajiv Gandhi Proudyogiki Vishwavidyalaya
Completed Date: 2012
Abstract: newline
Pagination: 30.0M.B.
URI: http://hdl.handle.net/10603/509823
Appears in Departments:Department of Electronic & Instrumentation

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File90.54 kBAdobe PDFView/Open
02_prelim pages.pdf2.44 MBAdobe PDFView/Open
03_contents.pdf404.07 kBAdobe PDFView/Open
04_abstrat.pdf109.9 kBAdobe PDFView/Open
05_ chapter 1 introduction.pdf1.13 MBAdobe PDFView/Open
06_ chapter 2 the opamp types,parameters and state of art.pdf4.91 MBAdobe PDFView/Open
07_chapter 3 design procedure for low power fast settling cmos opamp.pdf3.34 MBAdobe PDFView/Open
08_chapter 4 pole-zero placements for two-stage cmos opamp.pdf3.52 MBAdobe PDFView/Open
09_a chapter 5 analysis of compensation techniques for cmos opamp.pdf7.01 MBAdobe PDFView/Open
09_b chapter 6 modeling of the slewing behavior of three -stage cmos opamp.pdf1.87 MBAdobe PDFView/Open
09_c chapter 7 conclusions.pdf1.03 MBAdobe PDFView/Open
10_annexures.pdf2.54 MBAdobe PDFView/Open
80_recommendation.pdf2.44 MBAdobe PDFView/Open
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