Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/507299
Title: An optimal flip flop design for VLSI power minimization
Researcher: Gujjula, Nagarjuna Reddy
Guide(s): K., Rameshbabu
Keywords: 
Engineering
Engineering and Technology
Engineering Electrical and Electronic
Flip flop design
VLSI
University: Mewar University
Completed Date: 2022
Abstract: Available newline
Pagination: XIX, 138
URI: http://hdl.handle.net/10603/507299
Appears in Departments:Department of Electronic & Communication Engineering

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01_title.pdfAttached File29.49 kBAdobe PDFView/Open
02_prelim pages.pdf492.67 kBAdobe PDFView/Open
03_abstract.pdf198.26 kBAdobe PDFView/Open
04_contents.pdf125.07 kBAdobe PDFView/Open
05_chapter 1.pdf646.05 kBAdobe PDFView/Open
06_chapter 2.pdf588.03 kBAdobe PDFView/Open
07_chapter 3.pdf427.53 kBAdobe PDFView/Open
08_chapter 4.pdf1.54 MBAdobe PDFView/Open
09_chapter 5.pdf714.98 kBAdobe PDFView/Open
10_chapter 6.pdf974.59 kBAdobe PDFView/Open
11_chapter 7.pdf121.22 kBAdobe PDFView/Open
12_annexures.pdf2.23 MBAdobe PDFView/Open
80_recommendation.pdf150.37 kBAdobe PDFView/Open
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