1. Shodhganga@INFLIBNET
  2. Jaypee Institute of Information Technology
  3. Department of Electronics and Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/506475
Title: Power analysis and estimation of IP core based systems for FPGAs using machine learning techniques
Researcher: Singh, Neerja
Guide(s): Khare, Vijay and Verma, Gaurav
Keywords: Clock Enable,
Engineering
Engineering and Technology
Engineering Electrical and Electronic
Field Programmable Gate Arrays,
Intellectual Property,
Look-up-Tables, Flip-Flops
Power Estimation,
RTL,
University: Jaypee Institute of Information Technology
Completed Date: 2023
Abstract: included newline
Pagination: xxi, 152p.
URI: http://hdl.handle.net/10603/506475
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File172.47 kBAdobe PDFView/Open
02_prelim pages.pdf162.47 kBAdobe PDFView/Open
03_table of contents.pdf124.74 kBAdobe PDFView/Open
04_abstract.pdf82.22 kBAdobe PDFView/Open
05_chapter1.pdf427.46 kBAdobe PDFView/Open
06_chapter2.pdf399.96 kBAdobe PDFView/Open
07_chapter3.pdf651.95 kBAdobe PDFView/Open
08_chapter4.pdf665.1 kBAdobe PDFView/Open
09_chapter5.pdf1.4 MBAdobe PDFView/Open
10_chapter6.pdf507.96 kBAdobe PDFView/Open
11_annexures.pdf251.73 kBAdobe PDFView/Open
12_list of publications.pdf233.38 kBAdobe PDFView/Open
13_references.pdf236.8 kBAdobe PDFView/Open
14_synopsis.pdf253.58 kBAdobe PDFView/Open
80_recommendation.pdf208.09 kBAdobe PDFView/Open
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