Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/503191
Title: Low Power Design and Circuit Optimization by Leakage Power Reduction Techniques in Submicron CMOS Circuits
Researcher: Banu, Sufia
Guide(s): Gupta, Shweta
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Jain University
Completed Date: 2023
Pagination: 135 p.
URI: http://hdl.handle.net/10603/503191
Appears in Departments:Dept. of Electronics Engineering

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80_recommendation.pdfAttached File889.48 kBAdobe PDFView/Open
abstract.pdf232.1 kBAdobe PDFView/Open
annexures.pdf2.51 MBAdobe PDFView/Open
chapter 1.pdf863.32 kBAdobe PDFView/Open
chapter 2.pdf869.88 kBAdobe PDFView/Open
chapter 3.pdf1.38 MBAdobe PDFView/Open
chapter 4.pdf833.6 kBAdobe PDFView/Open
chapter 5.pdf963.32 kBAdobe PDFView/Open
chapter 6.pdf3.04 MBAdobe PDFView/Open
chapter 7.pdf593.03 kBAdobe PDFView/Open
cover page.pdf300.38 kBAdobe PDFView/Open
prelim pages.pdf771.04 kBAdobe PDFView/Open
table of contents.pdf317.43 kBAdobe PDFView/Open
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