Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/503191
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-07-31T08:42:11Z-
dc.date.available2023-07-31T08:42:11Z-
dc.identifier.urihttp://hdl.handle.net/10603/503191-
dc.format.extent135 p.
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleLow Power Design and Circuit Optimization by Leakage Power Reduction Techniques in Submicron CMOS Circuits
dc.title.alternative
dc.creator.researcherBanu, Sufia
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideGupta, Shweta
dc.publisher.placeBengaluru
dc.publisher.universityJain University
dc.publisher.institutionDept. of Electronics Engineering
dc.date.registered2019
dc.date.completed2023
dc.date.awarded2023
dc.format.dimensions
dc.format.accompanyingmaterialNone
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Dept. of Electronics Engineering

Files in This Item:
File Description SizeFormat 
80_recommendation.pdfAttached File889.48 kBAdobe PDFView/Open
abstract.pdf232.1 kBAdobe PDFView/Open
annexures.pdf2.51 MBAdobe PDFView/Open
chapter 1.pdf863.32 kBAdobe PDFView/Open
chapter 2.pdf869.88 kBAdobe PDFView/Open
chapter 3.pdf1.38 MBAdobe PDFView/Open
chapter 4.pdf833.6 kBAdobe PDFView/Open
chapter 5.pdf963.32 kBAdobe PDFView/Open
chapter 6.pdf3.04 MBAdobe PDFView/Open
chapter 7.pdf593.03 kBAdobe PDFView/Open
cover page.pdf300.38 kBAdobe PDFView/Open
prelim pages.pdf771.04 kBAdobe PDFView/Open
table of contents.pdf317.43 kBAdobe PDFView/Open


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