Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/503191
Title: | Low Power Design and Circuit Optimization by Leakage Power Reduction Techniques in Submicron CMOS Circuits |
Researcher: | Banu, Sufia |
Guide(s): | Gupta, Shweta |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Jain University |
Completed Date: | 2023 |
Pagination: | 135 p. |
URI: | http://hdl.handle.net/10603/503191 |
Appears in Departments: | Dept. of Electronics Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
80_recommendation.pdf | Attached File | 889.48 kB | Adobe PDF | View/Open |
abstract.pdf | 232.1 kB | Adobe PDF | View/Open | |
annexures.pdf | 2.51 MB | Adobe PDF | View/Open | |
chapter 1.pdf | 863.32 kB | Adobe PDF | View/Open | |
chapter 2.pdf | 869.88 kB | Adobe PDF | View/Open | |
chapter 3.pdf | 1.38 MB | Adobe PDF | View/Open | |
chapter 4.pdf | 833.6 kB | Adobe PDF | View/Open | |
chapter 5.pdf | 963.32 kB | Adobe PDF | View/Open | |
chapter 6.pdf | 3.04 MB | Adobe PDF | View/Open | |
chapter 7.pdf | 593.03 kB | Adobe PDF | View/Open | |
cover page.pdf | 300.38 kB | Adobe PDF | View/Open | |
prelim pages.pdf | 771.04 kB | Adobe PDF | View/Open | |
table of contents.pdf | 317.43 kB | Adobe PDF | View/Open |
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