Speed power and area efficient design of multiplier and adder for 2d fir digital filter

Abstract

Low power and high speed in very large scale integrated circuits has attracted the attention of researchers. Most of the computer arithmetic applications need highest degree of accuracy with good performance. Digital FIR filters are the fundamental signal processing operation used in signal, image and video applications. Adders and Multipliers are the basic arithmetic blocks used in integrated circuits. In this thesis, a high speed, low power and low area 2D FIR digital filter is designed and implemented in Xilinx FPGA. The multipliers like array, Booth, Wallace tree, and Vedic are used in the design of filters. Vedic multiplier is based on ancient mathematics. It uses a sutra called quotUrdhva Tiryabhyam to reduce the number of partial products in multiplication. Due to this, the speed of the multiplication process gets increased. Two efficient multipliers and one adder are proposed to optimize speed, area and power. The proposed multiplier is based on Vedic multiplier which uses a predictor block to predict the output in advance. Depending upon the previous outputs obtained, the current output is predicted. This multiplier increases the speed of multiplication when compared newline