Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/489575
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dc.coverage.spatial
dc.date.accessioned2023-06-07T06:29:54Z-
dc.date.available2023-06-07T06:29:54Z-
dc.identifier.urihttp://hdl.handle.net/10603/489575-
dc.description.abstractabstract available
dc.format.extentxxxiv, 137p.
dc.languageEnglish
dc.relation
dc.rightsself
dc.titleSome Approaches to Reduce the Bias Temperature Instability Related Aging Degradation of Logic Circuits
dc.title.alternative
dc.creator.researcherBhattacharjee, Abhishek
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guidePradhan, Sambhu Nath
dc.publisher.placeAgartala
dc.publisher.universityNational Institute of Technology Agartala
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2017
dc.date.completed2023
dc.date.awarded2023
dc.format.dimensions
dc.format.accompanyingmaterialCD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics and Communication Engineering

Files in This Item:
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01_title.pdfAttached File288.33 kBAdobe PDFView/Open
02_prelim pages.pdf838 kBAdobe PDFView/Open
03_content.pdf212.52 kBAdobe PDFView/Open
04_abstract.pdf188.06 kBAdobe PDFView/Open
05_chapter 1.pdf613.57 kBAdobe PDFView/Open
06_chapter 2.pdf883.68 kBAdobe PDFView/Open
07_chapter 3.pdf1 MBAdobe PDFView/Open
08_chapter 4.pdf1.37 MBAdobe PDFView/Open
09_chapter 5.pdf858.12 kBAdobe PDFView/Open
10_chapter 6.pdf897.43 kBAdobe PDFView/Open
11_chapter 7.pdf299.81 kBAdobe PDFView/Open
12_annexures.pdf386.45 kBAdobe PDFView/Open
80_recommendation.pdf584.7 kBAdobe PDFView/Open


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