Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/488271
Title: Vedic Mathematics Based Hardware Optimization for Various Arithmetic
Researcher: Patil, Avinash Subhash
Guide(s): Patil, Shailaja C.
Keywords: Electronics engineering
Engineering
Engineering and Technology
Engineering Electrical and Electronic
Hardware Optimization
Vedic Mathematics
University: Savitribai Phule Pune University
Completed Date: 2021
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/488271
Appears in Departments:JSPMs Rajarshi Shahu College of Engineering

Files in This Item:
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01_title.pdfAttached File987.79 kBAdobe PDFView/Open
02_prelim pages.pdf1.02 MBAdobe PDFView/Open
03_contents.pdf94.98 kBAdobe PDFView/Open
04_abstract.pdf75.9 kBAdobe PDFView/Open
05_chapter1.pdf320.6 kBAdobe PDFView/Open
06_chapter2.pdf117.45 kBAdobe PDFView/Open
07_chapter3.pdf998.11 kBAdobe PDFView/Open
08_chapter4.pdf1.14 MBAdobe PDFView/Open
09_chapter5.pdf292.78 kBAdobe PDFView/Open
10_chapter6.pdf512.28 kBAdobe PDFView/Open
11_chapter7.pdf274.21 kBAdobe PDFView/Open
12_chapter8.pdf59.02 kBAdobe PDFView/Open
13_annexures.pdf216.93 kBAdobe PDFView/Open
80_recommendation.pdf274.62 kBAdobe PDFView/Open
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