Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/484826
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DC FieldValueLanguage
dc.coverage.spatialDepartment of Electrical Engineering
dc.date.accessioned2023-05-23T07:45:56Z-
dc.date.available2023-05-23T07:45:56Z-
dc.identifier.urihttp://hdl.handle.net/10603/484826-
dc.description.abstractAbstract attached newline newline
dc.format.extentNA
dc.languageEnglish
dc.relationNA
dc.rightsuniversity
dc.titleEffective techniques for post silicon validation and debug
dc.title.alternativeNa
dc.creator.researcherKumar, Binod
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.noteNA
dc.contributor.guideSingh, Virendra
dc.publisher.placeMumbai
dc.publisher.universityIndian Institute of Technology Bombay
dc.publisher.institutionDepartment of Electrical Engineering
dc.date.registered2014
dc.date.completed2020
dc.date.awarded2020
dc.format.dimensionsNA
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electrical Engineering

Files in This Item:
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01_title.pdfAttached File98.34 kBAdobe PDFView/Open
02_prelimpages.pdf59.16 kBAdobe PDFView/Open
03_abstract.pdf54.5 kBAdobe PDFView/Open
04_contents.pdf313.75 kBAdobe PDFView/Open
05_chapter_1.pdf800.67 kBAdobe PDFView/Open
06_chapter_2.pdf367.53 kBAdobe PDFView/Open
07_chapter_3.pdf813.85 kBAdobe PDFView/Open
08_chapter_4.pdf685.13 kBAdobe PDFView/Open
09_chapter_5.pdf781.64 kBAdobe PDFView/Open
10_chapter_6.pdf666.76 kBAdobe PDFView/Open
11_chapter_7.pdf835.75 kBAdobe PDFView/Open
12_appendix.pdf197.15 kBAdobe PDFView/Open
80_recommendation.pdf152.62 kBAdobe PDFView/Open


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