1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Bombay
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/484826
Title: Effective techniques for post silicon validation and debug
Researcher: Kumar, Binod
Guide(s): Singh, Virendra
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Bombay
Completed Date: 2020
Abstract: Abstract attached newline newline
Pagination: NA
URI: http://hdl.handle.net/10603/484826
Appears in Departments:Department of Electrical Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File98.34 kBAdobe PDFView/Open
02_prelimpages.pdf59.16 kBAdobe PDFView/Open
03_abstract.pdf54.5 kBAdobe PDFView/Open
04_contents.pdf313.75 kBAdobe PDFView/Open
05_chapter_1.pdf800.67 kBAdobe PDFView/Open
06_chapter_2.pdf367.53 kBAdobe PDFView/Open
07_chapter_3.pdf813.85 kBAdobe PDFView/Open
08_chapter_4.pdf685.13 kBAdobe PDFView/Open
09_chapter_5.pdf781.64 kBAdobe PDFView/Open
10_chapter_6.pdf666.76 kBAdobe PDFView/Open
11_chapter_7.pdf835.75 kBAdobe PDFView/Open
12_appendix.pdf197.15 kBAdobe PDFView/Open
80_recommendation.pdf152.62 kBAdobe PDFView/Open
Show full item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: