1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology Bombay
  3. Department of Electrical Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/483554
Title: Application level synthesis to packet switched network overlays on FPGAs
Researcher: Kumar, Vinay B. Y.
Guide(s): Patkar, Sachin B.
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Indian Institute of Technology Bombay
Completed Date: 2019
Abstract: Abstract attached newline newline
Pagination: NA
URI: http://hdl.handle.net/10603/483554
Appears in Departments:Department of Electrical Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File403.16 kBAdobe PDFView/Open
02_prelimpages.pdf828.34 kBAdobe PDFView/Open
03_abstract.pdf79.1 kBAdobe PDFView/Open
04_contents.pdf218.33 kBAdobe PDFView/Open
05_chapter_1.pdf284.55 kBAdobe PDFView/Open
06_chapter_2.pdf748 kBAdobe PDFView/Open
07_chapter_3.pdf536.97 kBAdobe PDFView/Open
08_chapter_4.pdf610.73 kBAdobe PDFView/Open
09_chapter_5.pdf636.62 kBAdobe PDFView/Open
10_chapter_6.pdf297.99 kBAdobe PDFView/Open
11_chapter_7.pdf361.29 kBAdobe PDFView/Open
12_chapter_8.pdf429.34 kBAdobe PDFView/Open
13_annexure.pdf574.3 kBAdobe PDFView/Open
80_recommendation.pdf114.29 kBAdobe PDFView/Open
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