Modelling and simulation of short channel junctionless transistor from an analog design perspective

Abstract

Low power and high performance devices are in demand for today 8482 s microelectronics market Conventional planar CMOS transistors on bulk silicon substrate have been a key component in ultralarge scale integration technology for the past four decades but are approaching the fundamental physical limits imposed by short channel effects SCEs and gate oxide tunnelling Fully depleted multiple gatefield effect transistors Mug FETs was proposed as an alternative to planar devices because of thei