Shodhganga : a reservoir of Indian theses @ INFLIBNET
The Shodhganga@INFLIBNET Centre provides a platform for research students to deposit their Ph.D. theses and make it available to the entire scholarly community in open access.
Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/482052
| Title: | Security and testability issues in moders VLSI chips |
| Researcher: | Ahlawat, Satyadev |
| Guide(s): | Singh, Virendra |
| Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
| University: | Indian Institute of Technology Bombay |
| Completed Date: | 2019 |
| Abstract: | Abstract attached newline newline |
| Pagination: | NA |
| URI: | http://hdl.handle.net/10603/482052 |
| Appears in Departments: | Department of Electrical Engineering |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| 01_title.pdf | Attached File | 92 kB | Adobe PDF | View/Open |
| 02_prelimpages.pdf | 833.36 kB | Adobe PDF | View/Open | |
| 03_abstract.pdf | 81.72 kB | Adobe PDF | View/Open | |
| 04_contents.pdf | 182.83 kB | Adobe PDF | View/Open | |
| 05_chapter_1.pdf | 378.12 kB | Adobe PDF | View/Open | |
| 06_chapter_2.pdf | 344.7 kB | Adobe PDF | View/Open | |
| 07_chapter_3.pdf | 923.64 kB | Adobe PDF | View/Open | |
| 08_chapter_4.pdf | 900.29 kB | Adobe PDF | View/Open | |
| 09_chapter_5.pdf | 418.03 kB | Adobe PDF | View/Open | |
| 10_chapter_6.pdf | 734.59 kB | Adobe PDF | View/Open | |
| 11_annexure.pdf | 206.44 kB | Adobe PDF | View/Open | |
| 80_recommendation.pdf | 120.15 kB | Adobe PDF | View/Open |
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