Certain investigations on the endurance enhancement of non volatile memory in embedded systems using optimized learning algorithms and compression techniques

Abstract

The Non-Volatile Random Access Memory (NVRAM) is recently newlineidentified as the most upcoming main memory technology in Embedded and newlineInternet of Things (IoT) systems due to its appealing qualities like zero static newlinepower consumption and great memory cell density. As a result, mobile newlineapplications are becoming more powerful, but on the other side, it depends newlineon huge main memory, which takes a significant amount of system power. newlineThis difficulty is solved by switching to byte-addressable Non-Volatile newlineMemory (NVRAM) as the main memory. newlineOn the other hand, most NVRAMs have low write endurance due to newlineworkload-induced write variance, leading to more write activity at a few newlineblocks of memory than the other blocks. Improving the endurance of newlineNVRAM on embedded architectures is very critical due to the limited newlineconstraints of Embedded architectures in terms of size, speed, and newlinearchitecture pipelining. In addition, most embedded devices utilize integrated newlinesymmetric memory shared by multi-processors, which causes memory newlinedeficiency, less reliability, and reduced lifetime. newlineAdditionally, the energy consumption of Embedded devices depends newlineon two significant factors, execution time and average power consumed newlineduring the performance, which again depends on memory and processor. newlineDuring instruction execution, Embedded devices fail to execute their tasks newlinedue to a lack of memory accessibility, leading to poor performance. newlineSimilarly, delay increases due to a lack of memory read/write endurance newlinecycles. newline