Area and delay efficient fir filter design using multiplication optimization

Abstract

The finite impulse response filter is a key component of all digital video and image processing applications. Due to the higher sample operating rate of data processing, multimedia processors require more power. The major power consumption occurred by FIR filter operations. FIR filter consists of adders, multipliers and delay elements for processing filter inputs and co-efficients. The power consumption of the FIR filter is reduced or optimized by using different adder and multipliers architectures. The reduction in a number of multiplication and additions leads to better area reduction and speed improvements. The main aim of this research work is to propose new multiplier architectures and coefficient selection optimization algorithms to reduce a power consumption of the FIR filter design. newlineThis research work proposes four different FIR filter design approaches, 1) an odd and even stage based for FIR filter, 2) a modified computation sharing multiplier (CSHM) based FIR filter, 3) an optimized tree based MCM technique for FIR filter design and 5) a Differential Evolution (DE) based filter coefficient selection algorithm for FIR filter implementation. newlineMultiplication and addition are the most elementary operations in FIR filter implementation. The performance of the multiplier greatly effects the speed of the FIR filter. This work proposed an odd and even stage-based FIR filter implementation for low power applications. The ancient multiplier of vedic multiplier is used for coefficient and filter input multiplication. The proposed design analyzed in terms of slice, LUT and delay for various order of the filter. newline