Design and analysis of junction less finfet for low power and high frequency applications

Abstract

Advances in microelectronics have enabled smaller technical nodes, lower threshold voltages, and greater working frequencies. Even though VLSI circuit performance and power consumption have improved as a result, the reliability of the designs has suffered. A fall in noise resistance and an increase in uncertainty from multiple sources of variability make circuits more vulnerable as technology scales down. Fault tolerant techniques were commonly used in safety-critical applications. Three-dimensional electrical devices like double gate, tri-gate, and nanowire field-effect transistors (FETs) give an alternative approach since they regulate the device channel better electrostatically. Modern transistors have two metallurgical junctions, one at the source/channel region and the other at the drain/channel region. A strong doping profile at these junctions is required to scale semiconductor devices below 10 nm. Considering all possible attempts to improve gadget attributes, efforts had been put to develop new form of Fin Field Effect Transistor (FinFET). newlineIn this work, a new form of FinFET with asymmetric gate and source/drain connections is developed, and its simulation results were shown. Asymmetric FinFETs exhibit better short-channel behavior when the current density is increased, according to the results of the benchmarking. For applications in which conventional scaling has reached its physical limits, high aspect ratio FinFETs provide more current per area while requiring far less stringent horizontal geometry restrictions. newline