Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/478776
Title: Efficient low power design methodologies for implementing fft processor
Researcher: Padma Challa
Guide(s): P Jagadamba and P Ramana Reddy
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Jawaharlal Nehru Technological University, Anantapuram
Completed Date: 2022
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/478776
Appears in Departments:Department of Electronics and Communication

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01_title page.pdfAttached File36.2 kBAdobe PDFView/Open
02_prelimpages.pdf63.59 kBAdobe PDFView/Open
03_contents.pdf14.21 kBAdobe PDFView/Open
04_abstract.pdf13.16 kBAdobe PDFView/Open
05_chapter 1.pdf289.59 kBAdobe PDFView/Open
06_chapter 2.pdf82.24 kBAdobe PDFView/Open
07_chapter 3.pdf795.87 kBAdobe PDFView/Open
08_chapter 4.pdf1.39 MBAdobe PDFView/Open
09_chapter 5.pdf1.51 MBAdobe PDFView/Open
10_chapter 6.pdf625.48 kBAdobe PDFView/Open
11_chapter 7.pdf13.98 kBAdobe PDFView/Open
12_annexures.pdf63.46 kBAdobe PDFView/Open
80_recommendation.pdf41.56 kBAdobe PDFView/Open
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