1. Shodhganga@INFLIBNET
  2. Indian Institute of Technology IIT (BHU), Varanasi
  3. Electronics Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/478426
Full metadata record
DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-04-21T07:24:53Z-
dc.date.available2023-04-21T07:24:53Z-
dc.identifier.urihttp://hdl.handle.net/10603/478426-
dc.description.abstractAbstract is available in the attachment newline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleAnalytical Modeling and Simulation of Some Gate Structure Engineered Homo Heterojunction Double gate Tunnel FETs
dc.title.alternative
dc.creator.researcherKumar, Sanjay
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideJit, S.
dc.publisher.placeVaranasi
dc.publisher.universityIndian Institute of Technology IIT (BHU), Varanasi
dc.publisher.institutionElectronics Engineering
dc.date.registered2013
dc.date.completed2018
dc.date.awarded2018
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics Engineering

Files in This Item:
File Description SizeFormat 
01_title page.pdfAttached File93.73 kBAdobe PDFView/Open
02_preliminary pages.pdf2.1 MBAdobe PDFView/Open
03_content.pdf77.8 kBAdobe PDFView/Open
04_abstract.pdf235.28 kBAdobe PDFView/Open
05_chapter 01.pdf1.88 MBAdobe PDFView/Open
06_chapter 02.pdf1.61 MBAdobe PDFView/Open
07_chapter 03.pdf1.91 MBAdobe PDFView/Open
08_chapter 04.pdf2.15 MBAdobe PDFView/Open
09_chapter 05.pdf2.56 MBAdobe PDFView/Open
10_chapter 06.pdf279.01 kBAdobe PDFView/Open
11_annexure.pdf176.08 kBAdobe PDFView/Open
80_recommendation.pdf2.84 MBAdobe PDFView/Open
Show simple item record


Items in Shodhganga are licensed under Creative Commons Licence Attribution-NonCommercial-ShareAlike 4.0 International (CC BY-NC-SA 4.0).

Altmetric Badge: