Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/478071
Title: Development of novel optimization algorithms in cnn lstm networks for video analytics and fpga implementation
Researcher: Palanisamy P N
Guide(s): Malmurugan N
Keywords: Convolutional Neural Network
Distributed Filtering Structures
Field Programmable Gate Array
University: Anna University
Completed Date: 2022
Abstract: Deep Neural Network is a fascinating and popular research area in recent years and it plays an important role in video processing and analytics. Since, video analytics are primarily hardware centric, exploration of implementing the deep neural networks in the hardware, needs its brighter light of research. However, the computational complexity and resource constraints of deep neural networks are increasing exponentially with respect to time. Convolutional Neural Network (CNN) is one of the most popular deep learning architecture especially for image classification and video analytics. But this algorithm needs an efficient implementation strategy for incorporating more real time computations in terms of handling the videos in the hardware. Pruning methods find a way to optimize the network structure to suit them for hardware implementation. New pruning methods are the main focus of this research work for the hardware implementation which is expected to give better video analytics when combined with deep networks. newlineThis thesis proposes three optimization algorithms for pruning the network used for video analytics. The newly developed algorithms in this research work are Multi Objective Evolution Strategy (MOES) based pruning of Deep learning network, Novel pruning method using Zero Keep Filtering (ZKF) and Modified BAT (MBAT) algorithm based Pruning of Convolutional networks for processing the video in the hardware. newlineThe best algorithm investigated in this research work is implemented in the new shared Distributed Filtering Structures (DFS) for handling the filter layers in CNN with pipelined data-path in Field Programmable Gate Array (FPGA) newline
Pagination: xxviii,163p.
URI: http://hdl.handle.net/10603/478071
Appears in Departments:Faculty of Information and Communication Engineering

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01_title.pdfAttached File26.51 kBAdobe PDFView/Open
02_prelimpages.pdf3.49 MBAdobe PDFView/Open
03_contents.pdf334.09 kBAdobe PDFView/Open
04_abstracts.pdf211.24 kBAdobe PDFView/Open
05_chapter1.pdf636.48 kBAdobe PDFView/Open
06_chapter2.pdf400.05 kBAdobe PDFView/Open
07_chapter3.pdf1.13 MBAdobe PDFView/Open
08_chapter4.pdf1.11 MBAdobe PDFView/Open
09_chapter5.pdf1.32 MBAdobe PDFView/Open
10_chapter6.pdf509.69 kBAdobe PDFView/Open
11_annexures.pdf174.42 kBAdobe PDFView/Open
80_recommendation.pdf130.58 kBAdobe PDFView/Open
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