1. Shodhganga@INFLIBNET
  2. Shri Jagdishprasad Jhabarmal Tibarewala University
  3. Faculty of Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/477846
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-04-20T10:55:18Z-
dc.date.available2023-04-20T10:55:18Z-
dc.identifier.urihttp://hdl.handle.net/10603/477846-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titleLow power design using reversible coding in stacked binary counters and ternary content addressable memory
dc.title.alternative
dc.creator.researcherSanthi Chebiyyam
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideMoparthy Gurunadha Babu
dc.publisher.placeJhunjhunu
dc.publisher.universityShri Jagdishprasad Jhabarmal Tibarewala University
dc.publisher.institutionFaculty of Engineering
dc.date.registered2016
dc.date.completed2020
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Faculty of Engineering

Files in This Item:
File Description SizeFormat 
01_title.pdfAttached File155.09 kBAdobe PDFView/Open
02_prelim pages.pdf516.64 kBAdobe PDFView/Open
03_content.pdf336.08 kBAdobe PDFView/Open
04_abstract.pdf170.16 kBAdobe PDFView/Open
05_chapter 01.pdf615.64 kBAdobe PDFView/Open
06_chapter 02.pdf552.88 kBAdobe PDFView/Open
07_chapter 03.pdf1.13 MBAdobe PDFView/Open
08_chapter 04.pdf1.65 MBAdobe PDFView/Open
09_chapter 05.pdf1.05 MBAdobe PDFView/Open
10_chapter 06.pdf1.44 MBAdobe PDFView/Open
11_annexures.pdf339.04 kBAdobe PDFView/Open
80_recommendation.pdf213.15 kBAdobe PDFView/Open
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