Performance enhancement and Energy reduction in multi core Architecture with network on chip Interconnection

Abstract

With the rapid advancements in the semiconductor industry and newlinevarious VLSI-based applications, multi-core technology has evolved as a newlinehighly dominant field. A multi-core processor comprises numerous cores on a newlinesingle die. A multi-core processor supports parallel computation by newlineperforming thread-level parallelism thereby achieving faster execution of newlinetasks. A multi-core processor technology is widely used across many newlineapplication domains due to its improved speed and performance and newlinesupporting high-speed computing devices. The interconnectivity between the newlinecores of a multi-core architecture becomes a bottleneck with the bus-based newlinesystems. The Network-on-Chip (NoC) paradigm comes into the picture to newlineovercome the drawbacks involved in bus-based connectivity. The Intellectual newlineProperty (IP) cores of a multi-core architecture are connected through the newlinelinks, routers, and the Network Interface (NI). newlineThere are two kinds of multi-core processors namely homogeneous newlineand heterogeneous configurations. This classification is based on the type and newlinesize of the cores. A homogenous category has identical cores, and they are newlinereferred to as regular topologies. The salient features of a regular topology are newlineits fault tolerance and reusability. In the heterogeneous configuration also newlinecalled the irregular topology, the cores are of different sizes, and they are newlinedesigned for a particular application and hence they are referred to as newlineapplication specific topologies. newlineThere are many benefits that come with the multi-core processors newlinelike high speed and parallel computation thereby an improved performance newlinealong with the reduced time taken for the execution of the tasks newline