A hardware implementation of a Novel sms4 cipher algorithm and its Security evaluation encryption Efficiency analysis

Abstract

In this digital era, securing the data over the wireless channel is a newlinecrucial task. The importance of developing a cryptosystem to secure secret newlineinformation is increased rapidly based on the evolution in digitization. The newlinesectors like defense, medical, and banking, the lack of data security may newlineaffect human life and the economy. So, the cryptosystem should be secure and newlinefast enough to satisfy the requirements of such sectors. The intruder may try newlineto hack the data propagated through the unsecured wireless medium. newlineBrute-force is an attack that can break any cryptosystem by trying all the newlinepossible combinations. The strength of a cryptosystem relies on how much newlinetime the brute-force attack takes to decode the secret information. In the newlinedefense sector, the cryptosystem should be designed so that it should be more newlinevital to resist security attacks and be faster to encrypt the original message. newlineThe proposed SMS4-BSK cryptosystem is a symmetric cipher. The design is newlinedeveloped from the standard SMS4 algorithm. The encryption and decryption newlineprocess uses the same keyspace. The same architecture is also used for both newlineencryption and decryption. The SMS4-BSK cryptosystem is a block cipher newlinewith a block size of 128-bit. The input binary streams of the message is split newlineinto blocks. Each message block contains 128-bit. The cryptosystem is newlinecapable of processing 128-bit at a time. Both the encryption as well as key newlinegeneration architectures have 32 rounding operations. Confusion and newlinediffusion are deployed in each round to increase t he complexity of the design. newlineThe novel 32 round BSK processing block is developed to implement the newlinerounding operation in both the encryption and key generation architecture. newlineThe proposed algorithm is designed with Verilog HDL using the Xilinx ISE newlineDesign suite 14.6 tool. newline