Design and analysis of different Topologies in application specific Network on chip

Abstract

The embellishment and discovery of new procedures in interlinking newlineextensive Intellectual Property (IP) blocks in a System-on-Chip (SoC) is of newlineprime importance in this high-tech world. The interconnection in SoC is busbased newlinecommunication in which the performance is not up to the expectation newlinedue to non-coordination. Network-on-Chip (NoC) is the best solution for SoC newlineto achieve greater communication demands. All the network applications are newlinebased on NoC run-on Real-Time Operating System (RTOS). The nature of newlineRTOS is improvised in an advanced Reliable Reconfigurable Real-Time newlineOperating System (R3TOS) that supports NoC. The attributes such as newlineflexibility, scalability, and reliability are the prime characteristics of NoC that newlineoptimizes the power, area, and processing speed of the system. The Routing newlineElement (RE) is the primary functional block that connects the IP blocks in newlineNoC. Many standard topologies such as Mesh, Ring, Star, and Binary tree are newlineused to interconnect REs and IP blocks. newlineThe reusability feature of standard topology is best suitable for newlineNoCs in many applications. Simultaneously, it leads to poor performance in newlineApplication Specific NoC (ASNoC) in terms of more utilization of area, newlinepower, and latency, thus limiting its usage in ASNoC. For better performance newlineof ASNoC, designing an appropriately customized topology is more critical. newlineThe main feature of custom topology is the utilization of minimal resources newlinesuch as REs and interconnection links, which utilize less area and power newlineconsumption. Designing a custom topology is essential to standardize the newlineruntime problems such as reliability, fault tolerance, and reconfiguration by newlinegenerating a suitable scalable algorithm. newline