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http://hdl.handle.net/10603/4729
Title: | Algorithms and architectures for discrete Hartley transform |
Researcher: | Shah, Gautam A |
Guide(s): | Rathore, T S |
Keywords: | Discrete Hartley Transform Electronics and Telecommunications |
Upload Date: | 24-Sep-2012 |
University: | Narsee Monjee Institute of Management Studies |
Completed Date: | 26/07/2012 |
Abstract: | Discrete Hartley transform (DHT) is attractive mainly due to its real-valued kernel and identical forward and inverse transforms. This dissertation focuses two aspects of DHT: (i) development of fast algorithms, and (ii) development of architectures to implement the algorithms to compute DHT. The elements of the DHT matrix can be computed using the direct method in which each element of the matrix is computed based on its definition. Computationally fast position-based method is developed and implemented. In the method, the characteristics of the DHT matrix and its sub-matrix are identified. They are utilized to assign values to some elements, and compute only a few elements using the definition. These elements are then utilized to obtain the remaining elements based on their positions. An algorithm utilizing this method is developed which is faster in computing the elements than the direct method based on its definition. New radix-2 decimation-in-time and decimation-in-frequency algorithms are developed. Their distinct feature is that they explicitly introduce multiplying structures in the signal flow-diagram. The summing structures are modified to perform only addition and subtraction. They exhibit a signal flow-diagram with butterflies identical for each stage which make them suitable for implementation. The multiplying structures take care of all the multiplications and their related additions. The analytical expressions for the operation counts of these algorithms are derived and shown to require less number of multiplications. Similar exercise is carried for radix-4 DHT. It is found that radix-4 is faster than radix-2. The work is extended to develop the signal flow diagram of the split-radix DIT algorithm which utilizes combination of radix-2 and radix-4. Finally, a general-radix algorithm computes DHT for an arbitrary value of N, where either radix-4, radix-2 or the algorithm by definition is utilized.Basic analog circuits are designed to perform the summing structure and multiplying structure operations |
Pagination: | xii, 138p. |
URI: | http://hdl.handle.net/10603/4729 |
Appears in Departments: | Department of Electronic & Telecommunication Engineering |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | 80.61 kB | Adobe PDF | View/Open | |
02_certificate & declartions.pdf | 63.27 kB | Adobe PDF | View/Open | |
03_abstract.pdf | 77.98 kB | Adobe PDF | View/Open | |
04_acknowledgement.pdf | 149.95 kB | Adobe PDF | View/Open | |
05_contents.pdf | 86.41 kB | Adobe PDF | View/Open | |
06_list of figures tables & abbreviations.pdf | 108.95 kB | Adobe PDF | View/Open | |
07_chapter 1.pdf | 121.33 kB | Adobe PDF | View/Open | |
08_chapter 2.pdf | 256.76 kB | Adobe PDF | View/Open | |
09_chapter 3.pdf | 5.2 MB | Adobe PDF | View/Open | |
10_chapter 4c.pdf | 970.41 kB | Adobe PDF | View/Open | |
11_chapter 4b2.pdf | 104.15 kB | Adobe PDF | View/Open | |
12_chapter 5.pdf | 59.2 kB | Adobe PDF | View/Open | |
13_appendix A.pdf | 107.48 kB | Adobe PDF | View/Open | |
14_appendix B.pdf | 233.04 kB | Adobe PDF | View/Open | |
15_references.pdf | 86.45 kB | Adobe PDF | View/Open |
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