Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/4729
Title: Algorithms and architectures for discrete Hartley transform
Researcher: Shah, Gautam A
Guide(s): Rathore, T S
Keywords: Discrete Hartley Transform
Electronics and Telecommunications
Upload Date: 24-Sep-2012
University: Narsee Monjee Institute of Management Studies
Completed Date: 26/07/2012
Abstract: Discrete Hartley transform (DHT) is attractive mainly due to its real-valued kernel and identical forward and inverse transforms. This dissertation focuses two aspects of DHT: (i) development of fast algorithms, and (ii) development of architectures to implement the algorithms to compute DHT. The elements of the DHT matrix can be computed using the direct method in which each element of the matrix is computed based on its definition. Computationally fast position-based method is developed and implemented. In the method, the characteristics of the DHT matrix and its sub-matrix are identified. They are utilized to assign values to some elements, and compute only a few elements using the definition. These elements are then utilized to obtain the remaining elements based on their positions. An algorithm utilizing this method is developed which is faster in computing the elements than the direct method based on its definition. New radix-2 decimation-in-time and decimation-in-frequency algorithms are developed. Their distinct feature is that they explicitly introduce multiplying structures in the signal flow-diagram. The summing structures are modified to perform only addition and subtraction. They exhibit a signal flow-diagram with butterflies identical for each stage which make them suitable for implementation. The multiplying structures take care of all the multiplications and their related additions. The analytical expressions for the operation counts of these algorithms are derived and shown to require less number of multiplications. Similar exercise is carried for radix-4 DHT. It is found that radix-4 is faster than radix-2. The work is extended to develop the signal flow diagram of the split-radix DIT algorithm which utilizes combination of radix-2 and radix-4. Finally, a general-radix algorithm computes DHT for an arbitrary value of N, where either radix-4, radix-2 or the algorithm by definition is utilized.Basic analog circuits are designed to perform the summing structure and multiplying structure operations
Pagination: xii, 138p.
URI: http://hdl.handle.net/10603/4729
Appears in Departments:Department of Electronic & Telecommunication Engineering

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01_title.pdf80.61 kBAdobe PDFView/Open
02_certificate & declartions.pdf63.27 kBAdobe PDFView/Open
03_abstract.pdf77.98 kBAdobe PDFView/Open
04_acknowledgement.pdf149.95 kBAdobe PDFView/Open
05_contents.pdf86.41 kBAdobe PDFView/Open
06_list of figures tables & abbreviations.pdf108.95 kBAdobe PDFView/Open
07_chapter 1.pdf121.33 kBAdobe PDFView/Open
08_chapter 2.pdf256.76 kBAdobe PDFView/Open
09_chapter 3.pdf5.2 MBAdobe PDFView/Open
10_chapter 4c.pdf970.41 kBAdobe PDFView/Open
11_chapter 4b2.pdf104.15 kBAdobe PDFView/Open
12_chapter 5.pdf59.2 kBAdobe PDFView/Open
13_appendix A.pdf107.48 kBAdobe PDFView/Open
14_appendix B.pdf233.04 kBAdobe PDFView/Open
15_references.pdf86.45 kBAdobe PDFView/Open
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