Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/471634
Title: Design efficient algorithms to improve the hit ratio in high performance cache memory
Researcher: Srivastava, Swapnita
Guide(s): Singh, P. K.
Keywords: Cache memory
Computer architecture
Computer Science
Computer Science Software Engineering
Computer storage devices
Data transmission systems
Engineering and Technology
University: Madan Mohan Malaviya University of Technology
Completed Date: 2023
Abstract: File Attached newline
Pagination: xviii, 115p.
URI: http://hdl.handle.net/10603/471634
Appears in Departments:Computer Science and Engineering

Files in This Item:
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01_title.pdfAttached File314.62 kBAdobe PDFView/Open
02_prelim pages.pdf456.78 kBAdobe PDFView/Open
03_content.pdf187.88 kBAdobe PDFView/Open
04_abstract.pdf119.5 kBAdobe PDFView/Open
05_chapter 1.pdf1.26 MBAdobe PDFView/Open
06_chapter 2.pdf717.21 kBAdobe PDFView/Open
07_chapter 3.pdf2.65 MBAdobe PDFView/Open
08_chapter 4.pdf851.22 kBAdobe PDFView/Open
09_chapter 5.pdf5.07 MBAdobe PDFView/Open
10_chapter 6.pdf147.91 kBAdobe PDFView/Open
11_annexure.pdf924.19 kBAdobe PDFView/Open
80_recommendation.pdf392.01 kBAdobe PDFView/Open
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