Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/471634
Title: | Design efficient algorithms to improve the hit ratio in high performance cache memory |
Researcher: | Srivastava, Swapnita |
Guide(s): | Singh, P. K. |
Keywords: | Cache memory Computer architecture Computer Science Computer Science Software Engineering Computer storage devices Data transmission systems Engineering and Technology |
University: | Madan Mohan Malaviya University of Technology |
Completed Date: | 2023 |
Abstract: | File Attached newline |
Pagination: | xviii, 115p. |
URI: | http://hdl.handle.net/10603/471634 |
Appears in Departments: | Computer Science and Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 314.62 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 456.78 kB | Adobe PDF | View/Open | |
03_content.pdf | 187.88 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 119.5 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 1.26 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 717.21 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 2.65 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 851.22 kB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 5.07 MB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 147.91 kB | Adobe PDF | View/Open | |
11_annexure.pdf | 924.19 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 392.01 kB | Adobe PDF | View/Open |
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