Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/470997
Title: | Optimization of VlSI Floorplanning Problem |
Researcher: | AMARBIR SINGH |
Guide(s): | Leena Jain |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | I. K. Gujral Punjab Technical University |
Completed Date: | 2020 |
Abstract: | The number of electronic components in an Integrated Circuit (IC) has been newlineincreasing exponentially over the years. New technological advancements have newlineenabled engineers to build VLSI (Very Large Scale Integration) chip containing newlinemillions of transistors. Designing a VLSI circuit is a complex task as it involves high newlinepacking density and the requirement of high clock frequency makes this task even newlinemore complex. Due to these reasons, physical design automation plays a vital role in newlinedeveloping and fabricating a VLSI chip. newline |
Pagination: | All pages |
URI: | http://hdl.handle.net/10603/470997 |
Appears in Departments: | Department of Computer Applications |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 87.63 kB | Adobe PDF | View/Open |
02_prelim page.pdf | 446.71 kB | Adobe PDF | View/Open | |
03_content.pdf | 151.91 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 143.37 kB | Adobe PDF | View/Open | |
05_chapter1.pdf | 622.38 kB | Adobe PDF | View/Open | |
06_chapter2.pdf | 340.24 kB | Adobe PDF | View/Open | |
07_chapter3.pdf | 851.87 kB | Adobe PDF | View/Open | |
08_chapter4.pdf | 1.25 MB | Adobe PDF | View/Open | |
09_chapter5.pdf | 531.41 kB | Adobe PDF | View/Open | |
10_chapter6.pdf | 338.51 kB | Adobe PDF | View/Open | |
11_annexure.pdf | 378.88 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 195.53 kB | Adobe PDF | View/Open |
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