Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/470383
Title: | Latency Enhancement for DMesh Network on Chip Architecture with Cluster Routing |
Researcher: | Papalkar, Prajakta P |
Guide(s): | Gaikwad, Mahendra A |
Keywords: | Engineering and Technology Engineering Engineering Electrical and Electronic |
University: | Rashtrasant Tukadoji Maharaj Nagpur University |
Completed Date: | 2019 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/470383 |
Appears in Departments: | Electronics Engineering dept B D college of engineering Sewagram Wardha |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 316.89 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 382.12 kB | Adobe PDF | View/Open | |
03_content.pdf | 99.58 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 71.86 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 2.43 MB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 4.65 MB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 458.76 kB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 1.21 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 488.84 kB | Adobe PDF | View/Open | |
10_chapter 6.pdf | 994.13 kB | Adobe PDF | View/Open | |
11_annexure.pdf | 387.24 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 97.83 kB | Adobe PDF | View/Open |
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