Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/470383
Title: Latency Enhancement for DMesh Network on Chip Architecture with Cluster Routing
Researcher: Papalkar, Prajakta P
Guide(s): Gaikwad, Mahendra A
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
University: Rashtrasant Tukadoji Maharaj Nagpur University
Completed Date: 2019
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/470383
Appears in Departments:Electronics Engineering dept B D college of engineering Sewagram Wardha

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01_title.pdfAttached File316.89 kBAdobe PDFView/Open
02_prelim pages.pdf382.12 kBAdobe PDFView/Open
03_content.pdf99.58 kBAdobe PDFView/Open
04_abstract.pdf71.86 kBAdobe PDFView/Open
05_chapter 1.pdf2.43 MBAdobe PDFView/Open
06_chapter 2.pdf4.65 MBAdobe PDFView/Open
07_chapter 3.pdf458.76 kBAdobe PDFView/Open
08_chapter 4.pdf1.21 MBAdobe PDFView/Open
09_chapter 5.pdf488.84 kBAdobe PDFView/Open
10_chapter 6.pdf994.13 kBAdobe PDFView/Open
11_annexure.pdf387.24 kBAdobe PDFView/Open
80_recommendation.pdf97.83 kBAdobe PDFView/Open
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