Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/470089
Title: Modelling of Network on chip for improving quality of service
Researcher: Suryawanshi, Jaya R
Guide(s): Padole Dinesh V
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
University: Rashtrasant Tukadoji Maharaj Nagpur University
Completed Date: 2018
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/470089
Appears in Departments:Electronics engineering G H Raisoni College of Engineering

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01_title.pdfAttached File180.89 kBAdobe PDFView/Open
02_prelim pages.pdf351.83 kBAdobe PDFView/Open
03_content.pdf102.27 kBAdobe PDFView/Open
04_abstract.pdf85.03 kBAdobe PDFView/Open
05_chapter 1.pdf232.25 kBAdobe PDFView/Open
06_chapter 2.pdf186.01 kBAdobe PDFView/Open
07_chapter 3.pdf668.35 kBAdobe PDFView/Open
08_chapter 4.pdf1.28 MBAdobe PDFView/Open
09_chapter 5.pdf164.12 kBAdobe PDFView/Open
10_chapter 6.pdf771.54 kBAdobe PDFView/Open
11_annexures.pdf149.89 kBAdobe PDFView/Open
80_recommendation.pdf1.98 MBAdobe PDFView/Open
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