Nanowire Array based Gate All Around MOSFET Design for Future Generation Memory Devices

Abstract

This work proposes a novel device structure, the multi-channel silicon nanowire (SiNW) newlinegate all around (GAA) MOSFET, which is like the GAA structure but has multiple channels. newlineWith high performance indices in terms of large on/off-state current ratio (108), newlinelow Subthreshold Swing (64 mV/dec) and low threshold voltage (0.42V), this device newlineemerged itself as a contender for next generation memory devices. Although all these newlineperformance matrices are device dimension, physics, and numbers of channel dependent, newlinestill introducing multi-channel GAA MOSFET paving a path to next generation memory devices. Planar bulk MOSFET scaling is becoming increasingly difficult due newlineto increasing random variation in transistor performance with down scaling gate length, newlinemaking scaling of SRAM using minimum-size transistors even more difficult. A variety newlineof advanced MOSFET designs and their advantages for increasing the density and newlinevoltage scaling of SRAM arrays will be discussed in this dissertation. Transistor designs are optimized using 3-D design simulations. SRAM cell performance and yield newlinecan then be predicted using an analytic compact model calibrated to simulated transistor current-vs.-voltage characteristics. SiNW GAA MOSFET technology is expected to provide significantly better yield across a wide range of operating voltages than conventional bulk CMOS technology, in terms of cell area. Bulk silicon MOSFETs that are quasi-planar (QP) are a less expensive alternative that can also improve SRAM yield. newlineIn this thesis, a new multi-channel (nanowire array) based GAA MOSFET is proposed for next generation memory application. It is about incorporating multiple numbers of newlinenanowires as channels and the device performances were studied extensively. Comparative study also carried out for multi-channel rectangular GAA and cylindrical GAA newlineMOSFET. Apart from these, the device performance depends on number of channels newlinealso thoroughly investigated. This thesis describes a state-of-the-art SRAM with improved hold, read and write operation comp