Please use this identifier to cite or link to this item:
http://hdl.handle.net/10603/468256
Title: | Design of Asynchronous Viterbi decoder using minimum transition hybrid register exchange method for low power applications |
Researcher: | Tadse, Surekha K |
Guide(s): | Haridas, Sanjay L |
Keywords: | Engineering and Technology Engineering Engineering Electrical and Electronic |
University: | Rashtrasant Tukadoji Maharaj Nagpur University |
Completed Date: | 2018 |
Abstract: | newline |
Pagination: | |
URI: | http://hdl.handle.net/10603/468256 |
Appears in Departments: | Electronics engineering G H Raisoni College of Engineering |
Files in This Item:
File | Description | Size | Format | |
---|---|---|---|---|
01_title.pdf | Attached File | 208.13 kB | Adobe PDF | View/Open |
02_prelim pages.pdf | 299.83 kB | Adobe PDF | View/Open | |
03_content.pdf | 80.6 kB | Adobe PDF | View/Open | |
04_abstract.pdf | 271.4 kB | Adobe PDF | View/Open | |
05_chapter 1.pdf | 258.09 kB | Adobe PDF | View/Open | |
06_chapter 2.pdf | 191.59 kB | Adobe PDF | View/Open | |
07_chapter 3.pdf | 1.38 MB | Adobe PDF | View/Open | |
08_chapter 4.pdf | 1.29 MB | Adobe PDF | View/Open | |
09_chapter 5.pdf | 11.25 MB | Adobe PDF | View/Open | |
10_annexures.pdf | 126.34 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 4.77 MB | Adobe PDF | View/Open |
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