1. Shodhganga@INFLIBNET
  2. Rashtrasant Tukadoji Maharaj Nagpur University
  3. Electronics engineering G H Raisoni College of Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/468256
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-03-13T08:34:07Z-
dc.date.available2023-03-13T08:34:07Z-
dc.identifier.urihttp://hdl.handle.net/10603/468256-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsself
dc.titleDesign of Asynchronous Viterbi decoder using minimum transition hybrid register exchange method for low power applications
dc.title.alternative
dc.creator.researcherTadse, Surekha K
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideHaridas, Sanjay L
dc.publisher.placeNagpur
dc.publisher.universityRashtrasant Tukadoji Maharaj Nagpur University
dc.publisher.institutionElectronics engineering G H Raisoni College of Engineering
dc.date.registered2013
dc.date.completed2018
dc.date.awarded2020
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Electronics engineering G H Raisoni College of Engineering

Files in This Item:
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01_title.pdfAttached File208.13 kBAdobe PDFView/Open
02_prelim pages.pdf299.83 kBAdobe PDFView/Open
03_content.pdf80.6 kBAdobe PDFView/Open
04_abstract.pdf271.4 kBAdobe PDFView/Open
05_chapter 1.pdf258.09 kBAdobe PDFView/Open
06_chapter 2.pdf191.59 kBAdobe PDFView/Open
07_chapter 3.pdf1.38 MBAdobe PDFView/Open
08_chapter 4.pdf1.29 MBAdobe PDFView/Open
09_chapter 5.pdf11.25 MBAdobe PDFView/Open
10_annexures.pdf126.34 kBAdobe PDFView/Open
80_recommendation.pdf4.77 MBAdobe PDFView/Open
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