Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/468256
Title: Design of Asynchronous Viterbi decoder using minimum transition hybrid register exchange method for low power applications
Researcher: Tadse, Surekha K
Guide(s): Haridas, Sanjay L
Keywords: Engineering and Technology
Engineering
Engineering Electrical and Electronic
University: Rashtrasant Tukadoji Maharaj Nagpur University
Completed Date: 2018
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/468256
Appears in Departments:Electronics engineering G H Raisoni College of Engineering

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01_title.pdfAttached File208.13 kBAdobe PDFView/Open
02_prelim pages.pdf299.83 kBAdobe PDFView/Open
03_content.pdf80.6 kBAdobe PDFView/Open
04_abstract.pdf271.4 kBAdobe PDFView/Open
05_chapter 1.pdf258.09 kBAdobe PDFView/Open
06_chapter 2.pdf191.59 kBAdobe PDFView/Open
07_chapter 3.pdf1.38 MBAdobe PDFView/Open
08_chapter 4.pdf1.29 MBAdobe PDFView/Open
09_chapter 5.pdf11.25 MBAdobe PDFView/Open
10_annexures.pdf126.34 kBAdobe PDFView/Open
80_recommendation.pdf4.77 MBAdobe PDFView/Open
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