Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/467392
Title: Efficient on Chip Debugging Framework for Reconfigurable Soc Architectures
Researcher: Murali Anumothu
Guide(s): K Hari Kishore
Keywords: Engineering
Engineering and Technology
Engineering Electrical and Electronic
University: Koneru Lakshmaiah Education Foundation
Completed Date: 2021
Abstract: newline
Pagination: 
URI: http://hdl.handle.net/10603/467392
Appears in Departments:Department of Electronics and Communication Engineering

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01_titlepage.pdfAttached File92.24 kBAdobe PDFView/Open
02_decleration.pdf97.45 kBAdobe PDFView/Open
03_certificate.pdf97.78 kBAdobe PDFView/Open
04_acknowledgments.pdf92.86 kBAdobe PDFView/Open
05_abstract.pdf53.57 kBAdobe PDFView/Open
06_constents.pdf67.32 kBAdobe PDFView/Open
07_lst of figures.pdf127.21 kBAdobe PDFView/Open
08_list of tables.pdf116.31 kBAdobe PDFView/Open
09_list of acronyms.pdf51.04 kBAdobe PDFView/Open
10_chapter 1.pdf282.99 kBAdobe PDFView/Open
11_chapter 2.pdf196.67 kBAdobe PDFView/Open
12_chapter 3.pdf395.82 kBAdobe PDFView/Open
13_chapter 4.pdf528.5 kBAdobe PDFView/Open
14_chapter 5.pdf1.21 MBAdobe PDFView/Open
15_chapter 6.pdf1.25 MBAdobe PDFView/Open
16_chapter 7.pdf61.83 kBAdobe PDFView/Open
17_references.pdf238.31 kBAdobe PDFView/Open
18_list of publications.pdf230.43 kBAdobe PDFView/Open
80_recommendation.pdf5.18 MBAdobe PDFView/Open
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