Low Power Area Efficient and Reliable CNTFET Based SRAM Design for A Pacemaker Device

Abstract

Tremendous growth of the battery operated systems in recent years, made low power design a preeminence. Low power Static Random Access Memory (SRAM) design is examined as a major perturb of Wearable and Implantable devices like pacemakers, Hearing aids and Loop recorders, where the battery life is a key factor. Moreover, the role of SRAM is rapidly increasing as they are considered as an eminent block of System on Chips(SoCs). Major segment of SoCs is being occupied by SRAM because of its low power consumption and high speed. Since about 80% of the die area is tenanted by SRAM, the SoC s power consumption is greatly influenced by it. Therefore, there is an immense necessity to reduce the power consumed by SRAM at the time of its design. CMOS technology when scaled down to nanometer regime, for achieving high speed, low power consumption and high chip density made power dissipation a major challenge to the VLSI designers, as the leakage current is increased. Carbon NanoTube Field Effect Transistors (CNTFETs) are therefore turned out to be a promising alternative to the CMOS technology because of their good conductivity, high transport properties and high current drivability. newlineThe thesis concentrates on the design of SRAM Architecture with an array size of 1k cells with low power consumption and improved Read Noise Margin. SRAM array, the main block of the architecture consists of bit cells which are responsible for performing the Read, Write and Hold operations. Three different 9 transistors SRAM bit cells are proposed and discussed in this thesis with reduced leakage power as the Static power dissipation dominates the Dynamic power dissipation of SRAM since many of the cells remain in hold state. Apart from the leakage power reduction, the cells are designed in such a way to reduce the Dynamic power consumption also by making use of a single Bitline to perform the Write operation.