Hardware Neural Network Based Controller for Reduction of Rotor Oscillations

Abstract

Due to the inherent parallelism offered by the Artificial Neural Networks (ANNs) and newlinethe rapid growth of Field Programmable Gate Array (FPGA) technology, the implementation newlineof ANN in hardware (termed as Hardware Neural Network, HNN) for a complex control newlineproblem has become a promising trend. The basic design challenge in such a model is the newlineeffective utilization of FPGA resources and the high-speed reconfiguration of the ANN newlinecircuits. The updation of weights, changing the training patterns, replacing the activation newlinefunction and structure revision are generally termed as HNN reconfiguration . This process newlinecan be done either during the modelling phase or excecution phase. newlineIn the Modeling Phase Reconfiguration (MPR), the weights and connections are newlinedecided in the beginning itself and the same have been transformed to an equivalent newlinehardware on FPGA. Any sort of modification required during the processing period cannot newlinebe done unless otherwise the procedure is started from the beginning. The high level coding newlinedescribing ANN is to be re-generated, re-synthesized,placed and routed again. The advantage newlineof such an approach is that there is no need for an auxiliary logical circuit to permit external newlineprogramming of connection weights. But due to the frequent repetition of the algorithm from newlinethe beginning, the MPR is a time consuming process. Whereas, the excecution time newlinereconfiguration requires complex auxillary circuitary with sufficient interrupts to stop the newlineANN process at any time. The advantage of this method is the high speed reconstruction of newlineHNN. But, the identification of an appropriate neuron or layer for the pulse injection is a newlinecomplex procedure. newlineAt present, the pulses are either randomly applied to some selected neurons or applied newlineto all the neurons of the entire system. This results in the unwanted time delay and added newlineburden to the system.To address this issue, in this work, we have attempted to implement the newlinerun time reconfiguration with a systematic regulation algorithm called Dynam