VLSI Routing Algorithms for Timing Optimization

Abstract

newline In modern ASIC and FPGA design flow, global routing is a critical step. Implementation of an optimal procedure for global routing is essential as this directly impacts the performance of the chip. As we go deeper in sub-micron scaling and fabrication of a large number of transistors over a die, efficient EDA tools such as floorplanning, routing and placement become of utmost importance. FPGA Rapid prototyping of the electronic systems and their performance has been linked with routing directly and global routing has become an important parameter of the process yield. Therefore, there is a requirement to revisit the global routing methods during the design processing steps and to optimize performance of the electronic circuits post fabrication. In deep-sub-micron (DSM) regime, process variations become significant and can drastically affect the timing yield. It is well known that the process variations are spatial correlated. For pre-DSM technology nodes, in the absence of process variations, cells on a critical path are traditionally clustered to optimize the path delay. In this thesis, we report an empirical study in which we study the effect of net topology on the path delay in the presence of spatially correlated process variations.