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http://hdl.handle.net/10603/462691
Title: | Architecture Formulation of Multi Dimensional Clustering Algorithms for Image Analysis |
Researcher: | ANURADHA, M G |
Guide(s): | BASAVARAJ, L |
Keywords: | Engineering Engineering and Technology Engineering Electrical and Electronic |
University: | Visvesvaraya Technological University, Belagavi |
Completed Date: | 2021 |
Abstract: | The real world task such as audio and visual processing is carried out easily by the human brain. These functions are called Cognitive functions which need to be carried out artificially by a machine from the data samples collected. Clustering is one such machine learning cognitive function developed to realize the learning operations. newlineThe computations in the clustering algorithm are complex and iterative and hence implementation cost in terms of speed of the algorithm is a critical issue. To increase the performance of the learning algorithms, attempts are being made to implement these clustering algorithms using hardware like Graphic processing unit, Field programmable gate array and VLSI circuits as application specific Integrated circuits. There is a challenge on the hardware implementations as there is a requirement of high speed operation with low hardware resources and low power requirement.In the thesis, various architectures of these clustering algorithms are proposed and implemented on Virtex 6 FPGA which process or cluster the image at higher rate.The hardware architectures are built for On-line clustering algorithm, K-Means clustering algorithm and Mean shift algorithm. newlineThe first algorithm implemented is On-line clustering algorithm which is a two pass clustering algorithm. To avoid the memory overhead to store the input image, the moving average method calculating the mean of the cluster is used where the input data can be discarded after computation of the centroids. To speed up the clustering process, architecture for divider is proposed which can perform the division operation of the data varied up to 8 dimensions in one clock cycle. Due to pipeline approach, the throughput of one clock cycle is achieved. The architecture is implemented in Virtex 6 FPGA and the synthesized design shows that the maximum frequency is 45.9MHz and process 350 image frames in a second if the size of the image is 256X256 pixels. newline |
Pagination: | All Pages |
URI: | http://hdl.handle.net/10603/462691 |
Appears in Departments: | ATME College of Engineering Mysuru |
Files in This Item:
File | Description | Size | Format | |
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01_title.pdf | Attached File | 165.42 kB | Adobe PDF | View/Open |
02_certificate.pdf | 440.12 kB | Adobe PDF | View/Open | |
03_abstract.pdf | 1.58 MB | Adobe PDF | View/Open | |
04_declaration.pdf | 806.93 kB | Adobe PDF | View/Open | |
05_acknowledgement.pdf | 849.37 kB | Adobe PDF | View/Open | |
06_contents.pdf | 340.34 kB | Adobe PDF | View/Open | |
07_list of tables.pdf | 444.93 kB | Adobe PDF | View/Open | |
08_list of figures.pdf | 1.6 MB | Adobe PDF | View/Open | |
10_chapter 1.pdf | 1.23 MB | Adobe PDF | View/Open | |
11_chapter 2.pdf | 8.82 MB | Adobe PDF | View/Open | |
12_chapter 3.pdf | 992.97 kB | Adobe PDF | View/Open | |
13_conclusions.pdf | 1.25 MB | Adobe PDF | View/Open | |
14_bibliography.pdf | 655.23 kB | Adobe PDF | View/Open | |
80_recommendation.pdf | 400.17 kB | Adobe PDF | View/Open |
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