To Reduce the Power of On Chip Inter Connects Using Advanced VLSI Techniques

Abstract

Global market scenario is such that there is a continuous expectation of devices with more newlinefunctionality in less unit space. The competition in the market driving the design newlinecommunity for an aggressive technology challenges. This growth unfortunately, has an newlineimpact adversely on the global interconnects. As the millions of transistors fabricated on a newlinesingle chip and the die size is shrinking drastically, subsequently affecting the system newlineperformance. In an Integrated circuit (IC) speed is an important factor to be governed by newlinedevice design which is controlled by two components. First one, the transistor gate delay newlinewhich is switching time of an individual transistor and the second one is the gate delay, newlinewhich is due to signal propagation between two transistors. This gate delay is also taken newlineas interconnect delay. In earlier days this interconnects effects were neglected, but as the newlinedevice switching speed is limiting the performance of the system further it cannot be newlineneglected. newlineIn Very Large Scale Integration (VLSI) design flow the extraction of parasitic resistance newlineand capacitance in post lay out is an important stage. When the signals are dealing at newlineclock frequencies in Gigahertz range and with low resistivity copper connect and newlineinductance can no longer be neglected in the design. In an interconnect model the newlineresistance and capacitance has to be included but inductance effects are important only newlineunder certain conditions. newlineThe key metrics like propagation delay, power consumption as well as power delay newlineproduct are the parameters which determine the system performance. Interconnects newlineconsume more energy and also affects the propagation delay. In ICs once the energy newlinebudget is considered, the contribution from the interconnect wires and circuitries like newlinedrivers and receivers are more. In some designs the power dissipation from interconnects newlinenearly 40% of total on chip power dissipation. newlineIn this, total work is divided into two parts; first dealing with on chip interconnects the newlinePower Efficient Cloc