1. Shodhganga@INFLIBNET
  2. Sri Venkateswara University
  3. Department of Electronics & Communication Engineering
Please use this identifier to cite or link to this item: http://hdl.handle.net/10603/461958
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DC FieldValueLanguage
dc.coverage.spatial
dc.date.accessioned2023-02-18T08:24:08Z-
dc.date.available2023-02-18T08:24:08Z-
dc.identifier.urihttp://hdl.handle.net/10603/461958-
dc.description.abstractnewline
dc.format.extent
dc.languageEnglish
dc.relation
dc.rightsuniversity
dc.titlePerformance Enhancement of Approximate Wallace Tree Multiplier by Using Reversible Logic Gates in Inexact Compressor Adders
dc.title.alternative
dc.creator.researcherSudharani, B
dc.subject.keywordEngineering
dc.subject.keywordEngineering and Technology
dc.subject.keywordEngineering Electrical and Electronic
dc.description.note
dc.contributor.guideSreenivasulu, G
dc.publisher.placeTirupati
dc.publisher.universitySri Venkateswara University
dc.publisher.institutionDepartment of Electronics and Communication Engineering
dc.date.registered2015
dc.date.completed2021
dc.date.awarded2021
dc.format.dimensions
dc.format.accompanyingmaterialDVD
dc.source.universityUniversity
dc.type.degreePh.D.
Appears in Departments:Department of Electronics & Communication Engineering

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80_recommendation.pdfAttached File370.95 kBAdobe PDFView/Open
abstract.pdf187.5 kBAdobe PDFView/Open
bibliography.pdf2.86 MBAdobe PDFView/Open
chapter-1.pdf1.16 MBAdobe PDFView/Open
chapter-2.pdf320.46 kBAdobe PDFView/Open
chapter-3.pdf1.44 MBAdobe PDFView/Open
chapter-4.pdf1.53 MBAdobe PDFView/Open
chapter-5.pdf641.4 kBAdobe PDFView/Open
content.pdf316.23 kBAdobe PDFView/Open
prelims.pdf950.65 kBAdobe PDFView/Open
title.pdf465.73 kBAdobe PDFView/Open
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