Next generation nanoscale Double gate TFET with improved ambipolar and switching current performance

Abstract

The research work implemented here meant to expand the Tunnel field effect transistors newline(TFETs) operation in digital applications with enhanced device performance. Realization newlineof better TFET characteristics aims at developing new optimised TFET structure with newlinereduced ambipolar current (IAMB) and improved switching current (ION/IOFF) characteristics newlinesimultaneously. This improvement in switching current can be achieved by increasing ONcurrent newlinewithout hampering the OFF-current of the device. Along with that different device newlineparameter has been optimized to have a reduced ambipolar current, highest possible newlineswitching current (ION/IOFF) with a minimum average subthreshold swing (SSavg). newlineThis thesis proposes a way of improving the ON-current with ambipolar current reduction newlineof DG-TFET by implementing a new Z-shaped gate line TFET structure. Positioning of newlinegate over the source along with horizontal pocket (HP) insertion in the source region tries newlineto improve the tunneling area, thereby providing a boost in the ON-current with higher newlinesubthreshold swing of 45mV/dec. The proposed structure shows a significant improvement newlinein ON-current with maintained OFF and ambipolar current, so as to increases the newlineswitching current ratio. newlineFurther improvement in switching current ratio along with ambipolar reduction is proposed newlineby implementing splitted drain ZHP-TFET (SD-ZHP-TFET). The impact of different newlinedesign parameters influencing the performance of the structure, such as drain region-1 newlinethickness and the doping of drain region-1 and region-2 are studied extensively. Ef fect of newlinethese parameter variation on ambipolar current, switching current ratio and cut-off newlinefrequency has been studied in detail. The designed SD-ZHP-TFET is capable of reducing newlinethe ambipolar current up to OFF-current level. Finally, by taking the optimized device newlineparameters, we achieved excellent results of different performance parameters for the SDZHP- newlineTFET. Thus, the proposed DG Line-TFET model is a promising alternative for low newlinepower logic applications. The model accu